1. Field of the Invention
The invention relates to the field of electronic technique, particularly to an analog sample circuit with a switch circuit.
2. Description of Related Art
A switch capacitor circuit mainly includes a plurality of switch circuits controlled by corresponding clock signals and one or more capacitor and realizes various processes to electric signal by storing and transferring charge. In the practical circuit, the switch capacitor circuit mainly consisting of the switch circuits and the capacitor can't meet the requirement sometimes. Hence, the switch capacitor circuit usually combines with an amplifier, an operational amplifier or a comparator to realize generation, transformation and process of the electric signal.
A sampling hold circuit in a conventional analog sample circuit realizes various processes to the electric signal by using a Metal Oxide Semiconductor switch capacitor circuit usually. FIG. 1 is a circuit diagram exemplary showing a conventional analog sample circuit. Commonly, a chip in a standard CMOS (Complementary Metal Oxide Semiconductor) process has a minimum operating voltage of 0V and different maximum operating voltages (e.g. 1.8V, 2.5V, 3.3V, or 5V etc., 5V is used as the maximum operating voltage hereafter for simplicity) according to different processes. Referring to FIG. 1, the conventional analog sample circuit comprises four switch circuits SW1, SW2, SW3 and SW4, two capacitors Cs and Cint, and an operational amplifier A1. The circuit consisting of the switch circuits SW1, SW2, SW3 and SW4 and the capacitors Cs and Cint is the switch capacitor circuit mentioned above. A reference voltage REF is set to be half of the maximum operating voltage, namely 2.5V, for maximum signal amplitude. The reference voltage REF is also referred as a common mode voltage which is a middle voltage value for full differential signal. The common mode voltage is usually set to half of the maximum operating voltage for maximum signal amplitude. Clock signals driving the analog sample circuit is also shown in FIG. 1.
In operation, the switch circuits SW1 and SW3 turn on, the switch circuits SW2 and SW4 turn off, an input signal VIN is sampled by the capacitor Cs, and the capacitor Cint remains unchanged when the clock signal PH1 is high level “1” (5V). The switch circuits SW1 and SW3 turn off, the switch circuits SW2 and SW4 turn on, and the input signal is transferred from the capacitor Cs to the capacitor Cint for integration when the clock signal PH2 is high level “1”. The reference voltage REF is the common mode voltage of the input signal, so it is set to be 2.5V. The clock signal PH1 and the clock signal PH2 are a pair of non-overlapping clock signals.
In practical application, if the common mode voltage of the input signal is 0V, the analog sampling circuit may not work properly. The sample switch circuit of the analog sampling circuit in CMOS process is made up of single P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET), single N-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), or a pair of complementary PMOSFET and NMOSFET. If the common mode voltage of the input signal is 0V, the sample switch circuit made up of the PMOSFET doesn't turn on properly to sample the input signal because a gate-source voltage Vgs of the PMOSFET is larger than a threshold voltage Vth of the PMOSFET when a voltage of the input signal is less than 0V. If the common mode voltage of the input signal is 0V, the sample switch circuit made up of the NMOSFET also doesn't work properly because a PN junction of the NMOSFET is biased.
In order to solve the problem, a bias circuit is provided to generate a control level signal. The sample switch circuit turns on and off according to the control level signal. Thus, the analog signal lower than a minimum voltage in the circuit can be sampled properly. For example, FIG. 2 shows a circuit for sampling analog signal lower than a minimum voltage in the circuit disclosed in a Chinese patent published on May 16, 2007 with a publication number CN19641997A. Referring to FIG. 2, a turn-on voltage of the sample switch circuit is Vgs=Va−Vdd−Vin(n). For another example, FIG. 3 shows an analog sample circuit disclosed in a Chinese patent published on Jul. 26, 2006 with a publication number CN1266842C. Referring to FIG. 3, the turn-on voltage of the sample switch circuit is Vgs=Vin(n−1)−Vdd−Vin(n).
The turn-on voltage (namely the gate-source voltage Vgs) of the sample switch circuit is correlative to the input signal and changes with the input signal. As a result, an on resistance of the sample switch circuit also changes with the input signal. Thereby, the sampled signal may be distorted, and a high linear sample can't be realized.
Therefore, improved techniques for the analog sample circuit are desired to be provided to solve above problems.